//--
//-- One 1 ms, one pulse for 50mhz input clock
//-- 

module pulse_out(

input wire clk_in,  // 50mhz
input wire rst_n,

output 	reg 	pulse_10ms,
output 	reg 	wave_10ms,
output 	reg 	pulse_ms,
output 	reg 	wave_ms,
output 	reg 	pulse_100us,
output 	reg 	wave_100us,
output 	reg 	wave_1us,
output 	reg		pulse_test_out1,
output	reg		pulse_test_out2,
output	reg		pulse_test_out3,
output	reg		pulse_test_out4,
output	reg		pulse_test_out5,
output	reg		pulse_test_out6,
output	reg		pulse_test_out7
);

reg[17:0] cnt_0; // for pulse_ms
reg[17:0] cnt_1; // for pulse_10ms
reg[17:0] cnt_2; // for pulse_100us
reg[8:0] cnt_1us; // for wave_1us

//clk_in = 50M = 20nS, 20nS*25_000= 500uS = 0.5mS
always@(posedge clk_in or negedge rst_n) begin
	if(!rst_n) begin
		cnt_0[17:0] <= 18'h0;
	end
	else begin
		if(cnt_0[17:0] == 18'd24999) begin // 0.5ms
			cnt_0[17:0] <= 18'h0;
		end
		else  begin
			cnt_0[17:0] <= cnt_0[17:0] + 1'b1;
		end
	end
end

reg pulse_reg0;
reg pulse_reg1;

always@(posedge clk_in or negedge rst_n) begin
	if(!rst_n) begin
		wave_ms    <= 1'b0;
		pulse_reg0 <= 1'b0;
		pulse_reg1 <= 1'b0;
		pulse_ms   <= 1'b0;
	end
	else begin
		if(cnt_0[17:0] == 18'd24999) pulse_reg0 <= ~pulse_reg0;//invert the output at eatch 0.5mS ,1KHz
		
		pulse_reg1 <= ~pulse_reg0;
		
		pulse_ms <= pulse_reg0 & pulse_reg1; // 1 ms pulse,
		wave_ms  <= pulse_reg0;              // 1 ms wave
	end
end

//-------------------------------------------------------------
always@(posedge clk_in or negedge rst_n) begin
	if(!rst_n) begin
		cnt_1[17:0] <= 18'h0;
	end
	else begin
		if(cnt_1[17:0] == 18'd249999) begin // 5ms
			cnt_1[17:0] <= 18'h0;
		end
		else  begin
			cnt_1[17:0] <= cnt_1[17:0] + 1'b1;
		end
	end
end

reg pulse_reg2;
reg pulse_reg3;

always@(posedge clk_in or negedge rst_n) begin
	if(!rst_n) begin
		wave_10ms    <= 1'b0;
		pulse_reg2   <= 1'b0;
		pulse_reg3   <= 1'b0;
		pulse_10ms   <= 1'b0;
	end
	else begin
		if(cnt_1[17:0] == 18'd249999) pulse_reg2 <= ~pulse_reg2;
			
		pulse_reg3 <= ~pulse_reg2;
		
		pulse_10ms <= pulse_reg2 & pulse_reg3; // 10 ms pulse
		wave_10ms  <= pulse_reg2;              // 10 ms wave
	end
end

//-------------------------------------------------------------

always@(posedge clk_in or negedge rst_n) begin
	if(!rst_n) begin
		cnt_2[17:0] <= 18'h0;
	end
	else begin
		if(cnt_2[17:0] == 18'd2499) begin // 50us
			cnt_2[17:0] <= 18'h0;
		end
		else  begin
			cnt_2[17:0] <= cnt_2[17:0] + 1'b1;
		end
	end
end

reg pulse_reg4;
reg pulse_reg5;

always@(posedge clk_in or negedge rst_n) begin
	if(!rst_n) begin
		wave_100us    <= 1'b0;
		pulse_reg4   <= 1'b0;
		pulse_reg5   <= 1'b0;
		pulse_100us   <= 1'b0;
	end
	else begin
		if(cnt_2[17:0] == 18'd2499) pulse_reg4 <= ~pulse_reg4;
			
		pulse_reg5 <= ~pulse_reg4;
		
		pulse_100us <= pulse_reg4 & pulse_reg5; // 100us pulse
		wave_100us  <= pulse_reg4;              // 100us wave
	end
end

//-------------------------------------------------------------

always@(posedge clk_in or negedge rst_n) begin
	if(!rst_n) begin
		cnt_1us[8:0] <= 9'h0;
		wave_1us     <= 1'b0;
	end
	else begin
		if(cnt_1us[8:0] == 9'd249) begin // 5us
			cnt_1us[8:0] <= 9'h0;
			wave_1us <= ~wave_1us;
		end
		else  begin
			cnt_1us[8:0] <= cnt_1us[8:0] + 1'b1;
		end
	end
end


reg [7:0] cnt_us;
always@(posedge clk_in or negedge rst_n) begin
	if(!rst_n) begin
		cnt_us[7:0] <= 0;
	end
	else begin
		cnt_us = cnt_us + 1'b1;
	end
end

always@(posedge clk_in or negedge rst_n) begin
	if(!rst_n) begin
		pulse_test_out1 <= 0;
	end
	else begin
		if(cnt_us < 8'd128)//0.195MHz
			pulse_test_out1 <= 1'b0;
		else
			pulse_test_out1 <= 1'b1;
	end
end

always@(posedge clk_in or negedge rst_n) begin
	if(!rst_n) begin
		pulse_test_out2 <= 0;
	end
	else begin
		if((cnt_us % 64) == 0 )//0.390625MHz
			pulse_test_out2 <= ~pulse_test_out2;
		else
			pulse_test_out2 <= pulse_test_out2;
	end
end

always@(posedge clk_in or negedge rst_n) begin
	if(!rst_n) begin
		pulse_test_out3 <= 0;
	end
	else begin
		if((cnt_us % 32) == 0 )//0.78125MHz
			pulse_test_out3 <= ~pulse_test_out3;
		else
			pulse_test_out3 <= pulse_test_out3;
	end
end

always@(posedge clk_in or negedge rst_n) begin
	if(!rst_n) begin
		pulse_test_out4 <= 0;
	end
	else begin
		if((cnt_us % 16) == 0 )//1.5625MHz
			pulse_test_out4 <= ~pulse_test_out4;
		else
			pulse_test_out4 <= pulse_test_out4;
	end
end

always@(posedge clk_in or negedge rst_n) begin
	if(!rst_n) begin
		pulse_test_out5 <= 0;
	end
	else begin
		if((cnt_us % 8) == 0 )//50/16 = 3.125MHz
			pulse_test_out5 <= ~pulse_test_out5;
		else
			pulse_test_out5 <= pulse_test_out5;
	end
end

always@(posedge clk_in or negedge rst_n) begin
	if(!rst_n) begin
		pulse_test_out6 <= 0;
	end
	else begin
		if((cnt_us % 4) == 0 )//50/8 = 6.25MHz
			pulse_test_out6 <= ~pulse_test_out6;
		else
			pulse_test_out6 <= pulse_test_out6;
	end
end

always@(posedge clk_in or negedge rst_n) begin
	if(!rst_n) begin
		pulse_test_out7 <= 0;
	end
	else begin
		if((cnt_us % 2) == 0 )//50/4 = 12.5MHz
			pulse_test_out7 <= ~pulse_test_out7;
		else
			pulse_test_out7 <= pulse_test_out7;
	end
end

//-------------------------------------------------------------

endmodule